In recent years tremendous technological strides have been made in the area of high capacity memory storage. Such strides are best illustrated by semiconductor memory systems utilizing field effect transistors to store information therein in the form of capacitive charges. Such memories have great potential for use in inexpensive large capacity memory systems due to their small size, low power consumption and ease of fabrication as integrated circuits. However, this type of memory suffers from the disadvantage that the capacitive storage of information is essentially volatile and, accordingly, must be periodically restored or refreshed in order to maintain the viability of the stored information. Moreover, because such memories are often formed by combining a plurality of chips into arrays to form a plurality of memory planes, numerous decoders are required to indicate the column and row of the desired chip as well as the column and row of the desired cell in the chip to which access is desired. Because of the complexity of the semiconductor memories, the access circuits utilized to control access to the memories are also hard to diagnose. However, to ensure the operability of a semiconductor memory system, effective diagnosis must be made of the control circuitry therein to ensure that such control circuitry is applying the proper control signals to the semiconductor memory arrays. Several prior art arrangements as discussed below have been designed to diagnose such memories.
In one prior art arrangement as disclosed in J. A. Weisbecker U.S. Pat. No. 3,599,146, issued Aug. 10, 1971, each word stored in the semiconductor memory contained a parity bit indicating the parity over the address at which that word was stored. By first computing the actual parity over the outputs from the address register, and then by comparing that computed parity with the parity bit in the retrieved word, it could be ascertained whether the memory had been accessed at the proper address. This arrangement appears to be effective; however, the use of the memory for storage of additional diagnostic information is costly and the arrangement is limited to detecting addressing errors.
In another prior art arrangement disclosed in C. M. Nibby U.S. Pat. No. 3,814,922, issued June 4, 1974, a maintenance status register and associated apparatus were utilized to identify and store information relating to errors arising in a semiconductor memory module. This arrangement produced error correcting code signals for stored information, which code signals were also stored in the memory module. These stored error correcting code signals were then combined with the information signals to form a group of location identifying signals. This arrangement appears to be effective but like the abovementioned Weisbecker arrangement, the storage of diagnostic information is costly and, moreover it appears that complicated logic operations are required to detect malfunctions.
It is an object of this invention to perform effective and thorough, yet simple, diagnostic operations on the access circuits utilized to acess memory elements without storing any related diagnostic information in the memory; however, diagnostic information such as parity information may still be stored in the memory for use in other diagnostic operations.
It is a further object of this invention to perform such diagnostics on a noninterfering basis so that the error-free operation of the access circuits is verified without interfering with normal memory utilization.
It is a further object of this invention to use the refresh operation in semiconductor memories as a diagnostic tool.